1. Field of Invention
This invention relates generally to semiconductor memories and specifically to a method of programming a PMOS floating gate memory cell.
2. Description of Related Art
Conventional memories such as EEPROM and Flash EEPROM typically employ as a memory cell an N-channel floating gate transistor of the type shown in FIG. 1. The NMOS floating gate memory cell 10 is formed in a p-substrate 12 and includes an n+ source 14 and an n+ drain 16. A channel 18 extends within the substrate 12 between the n+ source 14 and the n+drain 16. A thin gate dielectric layer 20 separates a polysilicon floating gate 22 from the substrate 12. The gate dielectric 20 may be, for instance, a layer of silicon dioxide (SiO.sub.2), having a thickness of approximately 100 .ANG.. A second dielectric layer 24 separates a control gate 26 from the floating gate 22. Although not illustrated in FIG. 1, a protective insulating layer is typically formed over the cell 10, and electrical contacts are made to the n+ source 14, the n+ drain 16, and the control gate 26.
To program the cell 10, approximately 5 volts and 12 volts are applied to the drain 16 and the control gate 26, respectively, for a few milliseconds, while the source 14 is held at a low potential, e.g., ground potential. In response thereto, electrons accelerate across the channel 18 and, colliding with electrons and lattice atoms proximate the drain 16, generate hot electrons. The hot electrons are attracted to the high positive voltage on the control gate 26 and tunnel into the floating gate 22. The resulting accumulation of negative charge within the floating gate 22 increases the threshold voltage of the cell 10, thereby programming the cell 10.
The cell 10 may be erased by floating the drain 16, grounding the control gate 26, and applying approximately 12 volts to the source 14. Electrons within the floating gate 22 tunnel through the gate dielectric 20 and into the source 14, thereby restoring the threshold voltage to its original level and, thus, erasing the cell 10.
To read the cell 10, the source 14 is grounded, the drain 16 is held at between approximately 1 and 2 volts, and the control gate 26 is held at approximately 5 volts. Under these bias conditions, the cell 10 will conduct a channel current only if in an erased state.
Technological improvements have led to the development of a PMOS floating gate memory cell, as disclosed in the commonly owned and co-pending U.S. patent application Ser. No. 08/557,589 entitled "A PMOS Memory Cell with Hot Electron Injection Programming and Tunneling Erasing," filed Nov. 14, 1995, now issued as U.S. Pat. No. 5,687,118 to Chang and incorporated by reference herein. FIG. 2 illustrates a PMOS floating gate memory cell 30 of the type disclosed in the Chang patent. The cell 30 is formed in an n- well region 32 of a p- substrate 34. A p+ source 36 and a p+ drain 38 are formed in the n- well region 32. A channel region 40 extends within the n- well 32 between the p+ source 36 and the p+ drain 38. A polysilicon floating gate 42 is insulated from the n- well region 32 by a thin oxide layer 44. Preferably, the oxide layer 44 is approximately between 80-130 .ANG. thick and extends over the entire length of the channel region 40 and portions of both the p+ source 36 and the p+ drain 38. A control gate 46 is insulated from the floating gate 42 by an insulating layer 48. In its intrinsic state, the memory cell 30 has a threshold voltage V.sub.T of between approximately -1.5 and -2.0 volts.
The cell 30 may be programmed, for instance, by applying approximately 6.5 volts to the p+ source 36, grounding the p+ drain 38, and ramping the control gate 46 from a first voltage to a second voltage. These bias conditions cause positively charged holes to accelerate across the channel 40 towards the p+ drain 38. These accelerating holes collide with electrons and lattice atoms in a drain depletion region 50 proximate the p+ drain 38, thereby resulting in impact ionization. High energy electrons generated from the impact ionization are attracted to the ramped voltage on the control gate 46 and are thereby injected into the floating gate 42. The resultant negative charge on the floating gate 42 shifts the threshold voltage V.sub.T of the cell 30 to a more positive potential, thereby programming the cell 30.
To erase the cell 30, approximately 9 volts is applied to the p+ source 36, to the p+ drain 38, and to the n- well 32, while the control gate 46 is grounded. Electrons within the floating gate 42 tunnel through the oxide layer 44 and into the p+ source 36, the p+ drain 38, and the channel 40 of the cell 30, thereby returning the threshold voltage V.sub.T of the cell 30 to its normal level. This erasing technique is known as a channel erase.
The binary state of the cell 30 is read by applying, for instance, a supply voltage V.sub.CC of approximately 3 volts to the p+ source 36 and to the n- well 32. The control gate 46 is coupled to a potential between ground potential and V.sub.CC and the p+ drain 38 is coupled to a voltage slightly less than V.sub.CC. Under these bias conditions, the cell 30 conducts a channel current only if in a programmed state, i.e., only if the floating gate 42 is negatively charged. Thus, unlike NMOS memory cells, the PMOS memory cell 30 of FIG. 2 does not suffer from read disturb problems. The cell 30 is advantageous in numerous other ways over conventional NMOS memory cells, as discussed in the Chang patent.
However, in spite of the advantages realized by the recently developed PMOS floating gate memory cell, demand for faster programming speeds and higher endurance necessitates continual improvements in memory. Thus, it would be desirable to increase the speed with which a floating gate memory cell, e.g., cell 30, is programmed while also improving the endurance of the cell.